This week, Intel presents five papers at the 2022 IEEE Symposium on VLSI Technology & Circuits (VLSI) that describe the company’s progress on Intel 4, the semiconductor process technology formerly known as 7nm. Intel 4 is a transitional process for Intel. It is the first Intel process node that uses EUV (extreme ultraviolet, i.e. soft x-rays) lithography instead of deep-UV immersion lithography. The advances realized in the Intel 4 process sustain Moore’s Law by doubling the achievable transistor density relative to Intel 7, the process node formerly known as 10nm Enhanced Super Fin (10ESF). The Intel 4 process delivers a 20% performance gain relative to chips made with the Intel 7 process while running at the same power levels. Alternatively, you can get a 40% power reduction with Intel 4 at the same performance level achieved by the previous process node.
Intel has been on its competitive back foot for the last few years because Intel TD (Technology Development) postponed the use of EUV lithography longer than it should have. The idea was to delay the use of expensive EUV steppers for as long as possible to minimize manufacturing costs. By trying to stay with immersion lithography for just one more node, Intel 7, Intel lost performance parity with its main manufacturing competitors. Now the company is all in on EUV thanks to Pat Gelsinger’s aggressive stance. Intel 4 will be the company’s first production node to fully embrace EUV.
Ben Sell, a VP of TD at Intel, is the primary author on one of the five Intel 4 VLSI symposium papers, which is titled “Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High Performance Computing.” During a pre-event presentation, Sell said that in addition to reducing feature sizes, Intel 4 uses EUV to simplify the process technology by reducing the complexity and cost of creating each on-chip layer.
With the feature sizes being drawn, deep-UV immersion lithography requires multi-patterning to achieve the desired feature density. That’s because the drawn feature sizes are much smaller than the light wavelengths used. For the Intel 4 process, immersion lithography would need to expose the wafer through five different masks just to create one layer, while EUV requires only one mask thanks to the much shorter wavelengths of light being used. So even though an EUV process layer costs more than a layer created with immersion lithography, due to the immense acquisition and operating costs of an EUV stepper, the cost for one EUV process layer is less than the five passes required to make that same on-chip layer with immersion lithography.
The figure below summarizes some of the Intel 4 scaling improvements relative to Intel 7:
As the figure shows, individual features – including the contacted gate pitch, the fin pitch, and the interconnect pitch – have all shrunk. In addition, a previously announced innovation for this process node appears as pink cross-hatched rectangles in the figure above. Those rectangles represent “dummy gates,” which are required to electrically isolate adjacent FinFETs. With the transistor orientation shown in the above graphic, the dummy gates separate FinFETs positioned to the left and the right. Previous Intel process nodes required a pair of dummy gates per transistor, so there were two dummy gates interposed between each FinFET. For Intel 4, adjacent transistors share one dummy gate, which reduces the number of space-consuming separators by half.
Another major factor in the size reduction is due to the use of three fins per FinFET transistor for the Intel 4 process versus four fins per transistor for the Intel 7 process. (Fins appear as horizontal gray rectangles in the figure above.) Normally the use of fewer, smaller fins would degrade FinFET performance because, all other things being equal, fewer and thinner fins increase the transistor’s channel resistance. Ideally, that resistance should be as low as possible.
However, Sell explained that Intel 4 cuts the number of fins needed per transistor by using “enhanced copper” (cobalt-clad copper) to reduce trace impedance in the chip’s lower metal signal layers. Together with the additional capacitance reduction that results from scaling, Intel was able to reduce the number of fins per transistor in the Intel 4 cell library without hurting performance. The net result of these innovations is to double the number of transistors per square millimeter for chips made with Intel 4 relative to Intel 7. Doubling the number of transistors from one node to the next is the original definition of Moore’s Law.
Sell said that Intel Foundry Services (IFS) customers will have access to the Intel 4 process, but that IFS is really concentrating on the follow-on process node, Intel 3. He also said that chips developed for the Intel 4 process node would easily port to Intel 3, by design. Intel will use even more EUV lithography steps in the Intel 3 process and will create a denser high-performance cell library specifically for that process node.
However, the Intel 3 process node is, itself, an interim step. Intel 20A, the first of the company’s “Angstrom Era” nodes, will ditch the aging FinFETs in favor of the even more 3-dimensional RibbonFET transistors, which other semiconductor makers call GAA (gate all around) transistors. RibbonFETs will significantly boost transistor density yet again by stacking multiple transistor channels (ribbons) vertically on top of each other instead of laying channel fins down side by side as is done with FinFETs.
RibbonFETs exhibit improved transistor performance relative to FinFETs because the RibbonFET gate completely surrounds the channel. FinFET gates only contact the channel on three of four sides. Consequently, RibbonFET gates are better at controlling current flow through the transistor, which results in better performance. For reference, the much older planar FET gates contacted only one of the transistor channel’s four sides, so FinFETs represented a real improvement when they first appeared in production ten years ago.
Intel 20A will also be the company’s first process node to move the on-chip power distribution network (PDN) from the top of the chip to the bottom of the chip – the back side of the wafer – which should greatly reduce impedances and improve the PDN’s performance while simplifying signal routing on the chip’s top metal layers by making more room available for signal wires in the metal stack. Intel has dubbed this backside PDN technology “PowerVia,” which is a more expensive approach to creating a PDN because it requires the creation of nano TSVs (through-silicon vias) in the wafer. Innovations like RibbonFETs and PowerVia add process steps and therefore increase the manufacturing cost per wafer, but that’s the price to be paid for keeping Moore’s Law alive.
Sell said that the Intel 4 process will be ready for production in the second half of 2022. This process node is paired with Intel’s 14th-generation Meteor Lake client CPU architecture, which is scheduled to appear as shipping production chips in Q2 or Q3 of 2023. Intel will discuss Meteor Lake at the upcoming Hot Chips 34 conference in August. The Intel 4 process node will also be used to make compute tiles (chiplets) for the company’s Granite Rapids CPUs, which are aimed at data center servers.
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